(1) Field of the Invention
The present invention relates to the field of computer systems. More specifically, the present invention relates to a memory interface for interfacing between a local bus and a memory bus.
(2) Description of Related Art
Typically, computer systems utilize two address buses between a processor and a memory subsystem. One address bus is coupled to a static memory subsystem such as SRAM and ROM and the other address bus is coupled to a dynamic memory subsystem such as DRAM. Part of the reason for this implementation is that SRAM access requires only one address phase whereas DRAM access requires two address phases i.e., a phase in which the row address is asserted, and a second phase in which the column address is asserted. In other words, DRAM memories require a multiplexed address bus for rows and columns. Moreover, dynamic memory systems can be endowed with an interleaved memory scheme which provides even and odd memory banks. An interleaved bank is defined as a contiguous block of memory having independent odd and even leaves. Interleaving the odd and even leaves allows for higher system performance by overlapping CAS# (column address strobe) access times between leaves. Current memory controllers rely on separate even and odd address buses to support the dual leaves of an interleaved dynamic memory system. However, this addressing scheme that utilizes two address busses negatively impacts on the size of the chip and also requires a higher number of pins.
Furthermore, prior art systems are limited in their ability to implement long burst transactions as they provide at most the capability of transferring four words (1 quad word) during a burst transaction. These systems require thus for each quad word, an additional address phase, let alone additional recovery cycles and additional wait states between each shorter burst transaction. For computer systems using a Peripheral Component Interconnect (PCI) bus, which supports burst transactions of an extended length, it is desirable to provide an interface, between the PCI bus and the memory subsystem, which is capable of supporting long burst transactions without the overhead of asserting additional address phases and recovery cycles. The PCI bus is a high-speed I/O bus designed to define the interconnecting bus transfer protocol between highly-integrated peripheral adapters that are coupled to this bus. For more details regarding PCI system architecture, see PCI Local Bus Specification, Revision 2.1, of the PCI Special Interest Group of Portland, Oregon.
It is thus desirable to provide a computer system with a single address bus supporting both a static and a dynamic memory subsystem. Moreover, it is desirable to provide a single address bus which supports an interleaved dynamic memory system. It is also desirable to provide a memory interface supporting extended length burst transactions.